The present invention generally relates to metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically, to FINFET interconnect technology.
The MOSFET is a transistor used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary MOSFETs. The nFET uses electrons as the current carriers and with n-doped source and drain junctions. The pFET uses holes as the current carriers and with p-doped source and drain junctions.
In contrast to traditional planar metal-oxide-semiconductor, field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, non-planar FETs incorporate various vertical transistor structures. One such semiconductor structure is the “FINFET”, which takes its name from the multiple semiconductor “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width. Advantageously, the fin structure helps to control current leakage through the transistor in the off stage, and a double gate or tri-gate structure may be employed to control short channel effects.
The FINFET is a type of MOSFET. The FINFET is a double-gate or multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The “fin” refers to the narrow channel between source and drain regions. A thin dielectric layer on either side of the fin separates the fin channel from the gate.
Gate spacers form an insulating film along gate sidewalls. Gate spacers may also initially be formed around “dummy” gate sidewalls in replacement gate technology. The gate spacers are used to define source/drain regions in active areas of a semiconductor substrate located slightly away from the gate.
FINFET structures require the formation of fin structure through (1) formation of fins through an array of fins, also known as a sea of fins for CD control purpose and (2) removal of unwanted fins outside the active areas. When scaling the FINFET structures beyond the 10 nanometer (nm) node, the fin pitch is expected to be below 40 nm, making the removal of the fins (fins cut) challenging. As the fin pitch scales to a sub 40 nm dimension, the margin to completely remove the unwanted fins is very minimal, leaving with conventional fin cut approaches some silicon spikes.
Thus, there remains a need for an enhanced fin cut process, for example, for use during FINFET device fabrication, which does not leave unwanted fin residue or result in excessive semiconductor removal.